Efficient Implementation of Low Density Parity Check (LDPC) Decoder In VLSI

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Efficient Implementation of Low Density Parity Check (LDPC) Decoder In VLSI

Journal Title: International Journal of Electronics Communication and Computer Technology - Year 2012, Vol 2, Issue 4

Abstract

The best error-correcting performance can be achieved by using non-binary low-density parity check (NB-LDPC) codes. This can be of reduced decoding complexity with high cost efficiency and is mostly preferable than binary low density parity check codes. The proposed scheme not only reduces the computation complexity, but also eliminates the memory requirement for storing the intermediate messages generated from the forward and backward processes. A novel scheme and corresponding architecture are developed to implement the elementary step of the check node processing. In the design, layered decoding is applied and only nm<q messages are kept on each edge of the associated Tanner graph. The computation units and the scheduling of the computations are optimized in the context of layered decoding to reduce the area requirement and increase the speed. There by using this forward and backward process the memory requirement of the overall decoder can be substantially reduced. Thus to conclude that the above scheme leads to significant memory and complexity reduction inspired by the proposed check node processing scheme In addition, efficient architecture have been designed for the sorter and path constructor, and the computational scheduling has been optimized to further reduce the overall area and latency.

Authors and Affiliations

M. Revathy| Department of ECE, PSNA College of Engineering & Technology, Dindigul, India, Dr. R. Saravanan| Department of CSE, PSNA College of Engineering & Technology, Dindigul, India

Keywords

EP ID EP8295
DOI -
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