FPGA Based Low Power Design of an FIR Filter Using Distributed Arithmetic
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2017, Vol 5, Issue 4
Abstract
Standard wireless and mobile communication environments have huge demands on high speed signal processing operations. Finite Impulse Response (FIR) filter is one of the crucial factors in signal and image processing approaches. Traditional FIR filters have the advantage of linear phase, guaranteed stability, fewer finite precision errors and efficient implementation. However, they have a major disadvantage of requirements in higher order than Infinite Impulse Response (IIR) counterpart with comparable performance. Practical issues of higher order of FIR filters are more hardware requirements and power consumption when designing and fabricating the filter. In recent years, there are an increasing number of surveys being focuses on Distributed Arithmetic (DA) approaches for higher order digital FIR filter implementation. DA based multiplication is popular for its potential for efficient memory-based implementation. In this paper, we analyze the multiplier less DA multiplication approaches for higher order digital FIR filter. Many energy efficient DA architectures provide high speed and less area for performing multiplication operation which is absolutely suitable for higher order digital FIR filter implementation. Hence, DA based FIR filter effectively reduces the chip size, delay and power consumption due to storing the multiplication of input values and coefficients in memory as look-up-table (LUT). For reducing the hardware requirements and power consumption of higher order digital FIR filter, various level of DA multiplication approaches like memory based DA and pipeline based DA approaches are discussed and their performances are analyzed in this paper.
Authors and Affiliations
S. Venkatesh, K. Giri
Keywords
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- EP ID EP23775
- DOI http://doi.org/10.22214/ijraset.2017.4068
- Views 296
- Downloads 6
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