FPGA Implementation of Efficient Face Detector for Very Low Resolution Images
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2014, Vol 2, Issue 11
Abstract
Face detection is identifying or verifying the face from the input image. Face detection and tracking has been an active research area for a long time because it is the initial and important step in many different applications, such as video surveillance, face recognition, image enhancement, video coding. The proposed system provides good face detection of images that have low resolution. Applications like defence and security systems demand real time face Recognition systems, when other biometric techniques are not efficient. Eigen values are used in face recognition systems because they are sensitive for precision. Floating point operations are used in Eigen values but they are costly to implement on hardware. .Fixed point technique provides the flexibility in face recognition systems. This paper is implemented to provide solution for the [1] VLR (very low resolution problem) in face recognition which means the resolution of image is less than 16×16 those are captured from long distances. Existing face detection algorithms such as SR (super resolution) are not providing high performance image detection on very low resolution images. The proposed technique improves the resolution of the image by considering two phases1) the error measurement on high resolution image. 2) Training phase. The proposed architecture of RLSR based Face detection has been designed using Verilog HDL, simulated using Modelsim simulator and implemented on virtex 5 FPGA kit. Experimental results of the proposed technique shows the increased performance in terms of image quality and recognition accuracy. It is power efficient method and employed for portable applications.
Authors and Affiliations
P. Reshmika, M. V. Gnaneswara Rao
Keywords
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