FPGA Implementation OF Reed Solomon Encoder and Decoder
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2014, Vol 2, Issue 7
Abstract
Advanced communication techniques along with accuracy of information being very critical, the use of traditional Forward Error Correction (FEC) methods has become widespread. FEC provides a significant improvement to the system in terms of reliability of data reception. The basic principle behind error- correcting codes is the application of a mathematical transform onto the message signal such that redundant message information is used to correct any errors that may have been introduced during transmission. Reed Solomon Encoder and Decoder falls in the category of forward error correction encoders and it is optimized for burst errors rather than bit errors. Reed Solomon Encoder and Decoder provide a compromise between efficiency and complexity, so that this can be easily implemented using hardware or FPGA. FEC gives the receiver the ability to correct errors without needing a reverse channel to request retransmission of data, but at the cost of a fixed, higher forward channel bandwidth. FEC is therefore applied in situations where retransmissions are costly or impossible.
Authors and Affiliations
Kruthi. T. S, Mrs. Ashwini
Keywords
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