FPGA Implementation of Scalable Micro Programmed FIR Filter using Wallace Tree Multiplier
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2016, Vol 4, Issue 5
Abstract
Finite Impulse Response filters are the most important element in signal processing and communication. FIR filter architecture contain multiplier, adder and delay unit. So, performance of FIR filter is mainly based on multiplier. In this paper we present FIR filter implementation of Wallace multiplier. This technique is used to improve the performance of delay, power and Area. The code is written in VHDL and it is simulated in ModelSim 6.3c and synthesis is done in Xilinx ISE 9.2i. Finally the design is implemented in Spartan-3 FPGA.
Authors and Affiliations
K. Karthikeyan, K. Manivel
Keywords
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- EP ID EP22131
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