FPGA Implementation of Wallace Tree Multiplier using CSLA / CLA
Journal Title: UNKNOWN - Year 2013, Vol 2, Issue 12
Abstract
This paper discusses two different architectures of Wallace Tree Multiplier and analyses which one is better in respect of area and power consumption in order to fortify the multiplier design. In one of the architecture the final addition is performed using Carry look-ahead adder whereas in the other architecture the final addition is performed using Carry select adder. The proposed design in this paper is implemented on FPGA Spartan 3e and simulation tools used are Xilinx and Modelsim.
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