Design of Power Efficient and High Speed Carry Select Look Ahead Adder Using SP-D3l Logic

Journal title: The International Journal of Technological Exploration and Learning

Authors: K.Priyameenakshi| Assistant Professor, ECE Centre for Advanced research, Muthayammal Engg College Na...

Subject(s): Engineering, Educational Technology

Implementation of An Efficient Gate Level Modified Square-Root Carry Select Adder Using HDL

Journal title: International Journal of Science Engineering and Advance Technology

Authors: K.SURYA KUMARI| Assistant Professor, ECE, Pragathi Engineering College, (Affiliated to JNTUK, A.P),...

Subject(s): Engineering, Medicine, Social Sciences, Pharmacy

Area reduction in CSLA with efficient delay management

Journal title: International Journal of Science Engineering and Advance Technology

Authors: Ch Gayatri| Avant I institute of engineering & technology, Asst. prof..Avanthi institute of engineer...

Subject(s): Engineering, Medicine, Social Sciences, Pharmacy

Design and Implementation of Unsigned Multiplier Using COSA

Journal title: International Journal of Science Engineering and Advance Technology

Authors: S.Varaprasad Babu| PG Scholar, Dept of ECE, Nova College of Engineering, JNTUK, A.P, India, T.Babu R...

Subject(s): Engineering, Medicine, Social Sciences, Pharmacy

slugAN EFFICIENT CSLA ARCHITECTURE FOR VLSI HARDWARE IMPLEMENTATION

Journal title: International Journal of Management, IT and Engineering

Authors: Edison A.J and Mr. C. S. Manikandababu

Subject(s): Computer and Information Science, Engineering, Management Science, Development Studies

16 BIT UNSIGNED MULTIPLIER USING PROPOSED CSLA

Journal title: International Journal for Research in Applied Science and Engineering Technology (IJRASET)

Authors: Praveen B S, Manjunanth Badiger

Subject(s): Engineering, Applied Linguistics

Implementation of Unsigned Multiplier Using Area-Delay-Power Efficient Adder

Journal title: International Journal for Research in Applied Science and Engineering Technology (IJRASET)

Authors: Nalina R, Ashwini S S, Dr. M Z Kurian

Subject(s): Engineering, Applied Linguistics

Area Delay Power Efficient Carry Select Adder for Modern Signal Processors

Journal title: International Journal for Research in Applied Science and Engineering Technology (IJRASET)

Authors: Chandrabose. J, M. Ravikumar

Subject(s): Engineering, Applied Linguistics

AN EFFICIENT CSLA ARCHITECTURE FOR VLSI HARDWARE IMPLEMENTATION

Journal title: International Journal of Engineering, Science and Mathematics

Authors: Edison A.J and Mr. C. S. Manikandababu

Subject(s): Engineering, Mathematics

An efficient approach to minimize power and area in carry select adder using binary to excess one converter

Journal title: Acta Technica Napocensis- Electronica-Telecomunicatii (Electronics and Telecommunications)

Authors: T. CHELLADURA, V. MANIKANDAN, K. RAMAMOORTHY

Subject(s):

 Design and Implementation of High Speed Carry Select Adder

Journal title: INTERNATIONAL JOURNAL OF ENGINEERING TRENDS AND TECHNOLOGY

Authors: P.Prashanti

Subject(s):

 An Efficient Carry Select Adder with Less Delay and Reduced Area Application

Journal title: INTERNATIONAL JOURNAL OF ENGINEERING TRENDS AND TECHNOLOGY

Authors: Pandu Ranga Rao#1 Priyanka Halle

Subject(s):

 Performance Evaluation of Carry Select Adder-Review

Journal title: International Journal of Engineering Sciences & Research Technology

Authors: M.Priyadharshini

Subject(s):

Area Efficient Carry Select Adder (AE-CSLA) using Cadence Tools

Journal title: INTERNATIONAL JOURNAL OF ENGINEERING TRENDS AND TECHNOLOGY

Authors: Gagandeep Singh , Chakshu Goel

Subject(s):

FPGA Implementation of Wallace Tree Multiplier using CSLA / CLA