slugAN EFFICIENT CSLA ARCHITECTURE FOR VLSI HARDWARE IMPLEMENTATION

Journal Title: International Journal of Management, IT and Engineering - Year 2012, Vol 2, Issue 5

Abstract

Carry select adder (CSLA) is known to be the fastest adder among the conventional adder structures. Due to the rapidly growing mobile industry not only the faster arithmetic unit but also less area and low power arithmetic units are needed. The modified CSLA architecture has developed using Binary to Excess-1 converter (BEC). This paper proposes an efficient method which replaces the BEC using D latch. Experimental results are compared and the result analysis shows that the proposed architecture achieves the three folded advantages in terms of area, delay and power.

Authors and Affiliations

Edison A. J and Mr. C. S. Manikandababu

Keywords

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  • EP ID EP18341
  • DOI -
  • Views 287
  • Downloads 11

How To Cite

Edison A. J and Mr. C. S. Manikandababu (2012). slugAN EFFICIENT CSLA ARCHITECTURE FOR VLSI HARDWARE IMPLEMENTATION. International Journal of Management, IT and Engineering, 2(5), -. https://europub.co.uk/articles/-A-18341