General Algorithm for Testing the Combinational Logic Gates inside Digital Integrated Circuits
Journal Title: International Journal of engineering Research and Applications - Year 2017, Vol 7, Issue 7
Abstract
This article describes general algorithm used to build a tester for combinational logic gate(s) inside a digital Integrated Circuit (IC). The challenges include how to handle different type of gate, variant number of input, and cascaded gates. Proposed solution is using common function for all types of digital IC by interpreting defined data abstraction for combinational logic gate(s) inside digital IC. This data abstraction is written in simple array of byte to present pin numbers and gates. The solution has been verified by simulation using ISIS Proteus and in real condition where the algorithm is implemented on AVR microcontroller ATmega32. The result show that the algorithm works successfully to test all types of combinational logic gates inside TTL IC and CMOS IC as well.
Authors and Affiliations
Sidik Nurcahyo
Keywords
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- EP ID EP391594
- DOI 10.9790/9622-0707050105.
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