High-Rapidity and Power-Efficient Carry Skip Adder Performance with AOI and OAI Skip Logic
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2017, Vol 5, Issue 7
Abstract
In this paper compare to conventional one the new structure of adder contains high speed and uses less energy. The concatenation and the speed and the incrementation scheme can be applied to increase the speed and efficiency of the conventional carry skip adder structure. In CSKA structure the Multiplexer can be used as a skip logic. But in this structure it suggested to replace Multiplexer by the AOI (And Or Invert) OAI (Or And Invert) skip logic. The structure may contain both stages; one is Fixed size stage and another one is Variable size stage. Ultimately Hybrid Variable latency at extension of the suggested structure, which lesses the utilization0f the power without making an impact at the speed which is representing a speed.This extension utilizes amended parallel type structure , basically for segmenting the feeble time thus capaciting at the further reduction of voltage suggested structure are assesedby making a camparision of some parameter that is speed and power with other type of adders utilizing a forty nm static CMOS in technology for a extensive range of supply voltage.
Authors and Affiliations
AmrutaVarshini S H, Mr. S Pramod Kumar
Keywords
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