High Speed FIR Filter Based on Truncated Multiplier and Parallel Adder

Journal Title: INTERNATIONAL JOURNAL OF ENGINEERING TRENDS AND TECHNOLOGY - Year 2013, Vol 5, Issue 5

Abstract

High speed Finite Impulse Response filter (FIR) is designed using the concept of faithfully rounded truncated multiplier and parallel prefix adder. The bit width is also optimized without sacrificing the signal precision. A transposed form of FIR filter is implemented using an improved version of truncated multiplier and parallel prefix adder. Multiplication and addition is frequently required in Digital Signal Processing. Parallel prefix adder provides a high speed addition and the improved version of truncated multiplier also provides successive reduction in delay and the components used

Authors and Affiliations

Deepshikha Bharti , K. Anusudha

Keywords

Related Articles

An Area Efficient (31, 16) BCH Decoder for Three Errors

Bose, Ray- Chaudhuri, Hocquenghem (BCH) codes are one of the efficient error-correcting codes used to correct errors occurred during the transmission of the data in the unreliable communication mediums. This paper presen...

 KINEMATIC ANALYSIS OF 3 D.O.F OF SERIAL ROBOT FOR INDUSTRIAL APPLICATIONS

 The paper address the study of motion can be divided into kinematics and dynamics. Direct kinematics refers to the calculation of end effectors position, orientation, velocity, and acceleration when the corres...

 Load Compensation by Diesel Generator and Three Level Inverter Based DSTATCOM

 This paper presents the load compensation by diesel generator. In this compensation reactive power, harmonics and unbalanced load current generates because of linear or nonlinear loads. The control of Distribution...

Gender Recognition from Model’s Face Using SVM Algorithm

This paper presents a method for Gender Recognition using Support Vector Machine (SVM).This System consists of two stages – Feature Extraction and SVM Classification. In Feature Extraction we separate out eyes nose and m...

Area Efficient Carry Select Adder (AE-CSLA) using Cadence Tools

To perform fast addition operation, CSLA is one of the fastest adders used in many data-processing processors. Analyzing the structure of Regular CSLA (R-CSLA) and Modified CSLA (M-CSLA), there is a scope to reduce the a...

Download PDF file
  • EP ID EP120694
  • DOI -
  • Views 114
  • Downloads 0

How To Cite

Deepshikha Bharti, K. Anusudha (2013). High Speed FIR Filter Based on Truncated Multiplier and Parallel Adder. INTERNATIONAL JOURNAL OF ENGINEERING TRENDS AND TECHNOLOGY, 5(5), 243-247. https://europub.co.uk/articles/-A-120694