IMPLEMENTATION OF ADIABATIC LOGIC CIRCUIT FOR LOW POWER APPLICATION
Journal Title: International Journal of Electrical, Electronics and Mechanical Fundamentals (www.ijeemf.com) - Year 2012, Vol 3, Issue 1
Abstract
This paper is concerned with the Implementation of Adiabatic Logic Circuit for Low Power Application with technology improvement; power dissipation in computer hardware has become one of the most important factors. It is well known that the short-circuit dissipations, leakage dissipations and dynamic switching power dissipations are three main components of power consumptions in CMOS chips. The focus of the research presented will be a detailed study of the CMOS logic circuit and the power dissipation in the CMOS logic circuit. A mathematical expression has been developed to explain the energy dissipation in our adiabatic inverter circuit. Two Adiabatic Logic families are explained. One is the Positive Feedback Adiabatic Logic (PFAL), and the other is the Efficient Charge Recovery Logic (ECRL). Both share the property, that they are operated with a four-phase power-clock. Effective Charge Recovery Logic (ECRL) has been proposed. They all obtained significant dynamic energy dissipations savings by recycling the energy stored in circuit nodes. In Simulation Results shows the Performance of Adiabatic inverter, NAND gate, NOR gate and full adder using P-Spice. And it shows the comparative result for power dissipation and Delay with different logic circuit with different frequency
Authors and Affiliations
Varinder Kumar , Mr. Narender Kumar
Keywords
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