Implementation of Area Efficient and High Bit Rate Serial-Serial Multiplier With On-the-Fly Accumulation by Asynchronous Counters
Journal Title: International Journal of Science Engineering and Advance Technology - Year 2014, Vol 2, Issue 9
Abstract
Traditional Serial-Serial multiplier addresses the high data sampling rate. It is effectively considered as the entire partial product matrix with n data sampling cycle for n×n multiplication function instead of 2n cycles in the conventional multipliers. This multiplication of partial products by considering two series inputs among which one is starting from LSB the other from MSB. Using this feed sequence and accumulation technique it takes only n cycle to complete the partial products. It achieves high bit sampling rate by replacing conventional full adder and highest 5:3 counters. Here asynchronous 1’s counter is presented. This counter takes critical path is limited to only an AND gate and D flipflops. Accumulation is integral part of serial multiplier design. 1’s counter is used to count the number of ones at the end of the nth iteration in each counter produces. The implemented multipliers consist of a serial-serial data accumulator module and carry save adder that occupies less silicon area than the full carry save adder. In this paper we implemented model address for the 8bit 2’s complement implementing the Baugh-wooley algorithm and unsigned multiplication implementing the architecture for 8×8 Serial-Serial unsigned multiplication.
Authors and Affiliations
Suda Sriram| M.Tech, Embedded Systems. Joggaih Institute of Tech. & Engg. College of Engineering. Kalagampudi, West Godavari District. Andhra Pradesh, India. sriramsuda@gmail.com, Ch. Kanakalingeswara Rao| Assistant Professor in ECE dept. Joggaih Institute of Tech. & Engg. College of Engineering. Kalagampudi, West Godavari District. Andhra Pradesh, India. klr_mani786@yahoo.co.in
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