Implementation of DSP architecture for LMS
Journal Title: International Journal of engineering Research and Applications - Year 2017, Vol 7, Issue 8
Abstract
In this paper we have used Urdhva Tiryakbhyam Multipliers method in arithmetic logic unit with carry select adder, high speed Vedic Multiplication techniques of Ancient Indian Vedic Mathematics that have been modified to improve performance of conventional arithmetic logic unit. Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on sixteen Sutras. We have done study on efficiency of Urdhva Triyagbhyam – Vedic method for multiplication which strikes a difference in the actual process of multiplication itself. It eliminates unwanted multiplication steps with zeros and scaled to higher bit levels using Karatsuba algorithm with the compatibility to different data types. Urdhva tiryakbhyam Sutra is most efficient Sutra method, provide minimum processing delay for multiplication of all types of numbers, either small or large. In this project we will implement DSP architecture method in Xilinx to perform LMS algorithm.
Authors and Affiliations
Hiba Khan, Mr. Rakesh Mandliya
Keywords
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- EP ID EP392067
- DOI 10.9790/9622-0708053740.
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