Implementation Of Radix-10 Matrix Code Using High Speed Adder For Error Correction
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2016, Vol 5, Issue 5
Abstract
Memories are most widely used component in electronic systems. As CMOS technology scales down, multiple cell upsets (MCUs) are causing series issues in memory reliability. In order to protect data in memory, error detection and correction codes are used. The problem with existing error correction codes is that they are either single or double error correction codes. To overcome this issue, a radix-10 based matrix code can be used for multiple error detection to protect memory. This system uses an encoder and decoder section. In this paper, this approach further optimizes the delay with the use of fast adders like parallel prefix carry look ahead adder. A Comparison of radix-10 matrix code using different types of adders was made in order to reduce the delay. The design was modeled using verilog, simulated and synthesized using Xilinx ISE 14.7 and Cadence.
Authors and Affiliations
Grace Abraham, Nimmy M Philip, Deepa N R
Keywords
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