Improved Design of Low Power TPG Using LP-LFSR
Journal Title: International Journal of Computer & organization Trends(IJCOT) - Year 2013, Vol 3, Issue 4
Abstract
This paper presents a novel test pattern generator which is more suitable for built in self test (BIST) structures used for testing of VLSI circuits. The purpose of the BIST is to reduce power dissipation without affecting the fault coverage. The demonstrated test pattern generator reduces the switching activity among the test patterns at the most. In this method, the single input change patters generated by a counter and a gray code generator are Exclusive–ORed with the seed generated by the low powerl inear feedback shift register[LP-LFSR]. The proposed schemeis evaluated by using a 4x4 Braun array multiplier. TheSystem-On-Chip(SOC) approach is adopted for implementation on Alter a Field Programmable Gate Arrays(FPGAs) based SOC kits with Nios II soft-core processor. From the implementation results, it is verified that the testing power for the proposed method is reduced by a significant percentage.
Authors and Affiliations
Praveen Kasunde , Dr. K B ShivaKumar , Dr. M Z Kurian
Keywords
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- EP ID EP93785
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