Logical Design of Quaternary Signed Digit Conversion Circuit and its Effectuation using Operational Amplifier
Journal Title: Bonfring International Journal of Power Systems and Integrated Circuits - Year 2012, Vol 2, Issue 4
Abstract
In binary number system carry is a major problem in arithmetical operation. We have to suffer O(n) carry propagation delay in n-bit binary operation. To overcome this problem signed digit is required for carry free arithmetical operation. Further, literature reviews suggest that multi-valued logic (MVL) would be a better choice to address the problem of developing faster chips for performing faster computational operation. Quaternary Signed Digit (QSD) have a major contribution in higher radix (=4) carry free arithmetical operation. For digital implementation, the signed digit quaternary numbers are represented using 3-bit 2's compliment notation. In this paper, a simple and new technique of binary (2's compliment) to QSD conversion is proposed and described. Well-known operational amplifier (OPAMP) based digital to analog converter circuit is also given to verify the above technique.
Authors and Affiliations
Tanay Chattopadhyay , Tamal Sarkar
Keywords
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- EP ID EP146117
- DOI 10.9756/BIJPSIC.3130
- Views 126
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