Low Latency NoC Router Micro Architecture using Dynamic Virtual Channel Organization

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Low Latency NoC Router Micro Architecture using Dynamic Virtual Channel Organization

Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2017, Vol 5, Issue 4

Abstract

The number of cores on a chip is rapidly increased the on chip need an efficient communication structure as network on chip (NoC). The channel buffer organization of NoC uses virtual channels (VCs) to improve data flow and performance of the NoC system. Dynamically allocated multi queues are an good mechanism to reach VC flow control with maximum no of buffer utilization. In this design, VCs employ variable number of buffer slots depending on the network traffic. we propose a new input port micro architecture to cooperate our efficient dynamic VC (EDVC) approach that is built on DAMQ buffers. To show the advantages of EDVC, we compare its micro-architecture with that of the traditional dynamic VC (CDVC), it’s also employs link-list tables for buffer organization. In terms an hardware, EDVC input-port organization consumes on average 51% less power for ASIC design when compared with the CDVC input port. The saving is even good when compared with VC regulator methodology. This EDVC approach can improve NoC latency by 38%–48% and throughput by 100% on average as compared with the CDVC mechanism. The proposed design parameters are analyzed using Xilinx 9.1.

Authors and Affiliations

Praveen M, Mothi. R

Keywords

EP ID EP23922
DOI http://doi.org/10.22214/ijraset.2017.4216
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