Low Latency NoC Router Micro Architecture using Dynamic Virtual Channel Organization

Abstract

The number of cores on a chip is rapidly increased the on chip need an efficient communication structure as network on chip (NoC). The channel buffer organization of NoC uses virtual channels (VCs) to improve data flow and performance of the NoC system. Dynamically allocated multi queues are an good mechanism to reach VC flow control with maximum no of buffer utilization. In this design, VCs employ variable number of buffer slots depending on the network traffic. we propose a new input port micro architecture to cooperate our efficient dynamic VC (EDVC) approach that is built on DAMQ buffers. To show the advantages of EDVC, we compare its micro-architecture with that of the traditional dynamic VC (CDVC), it’s also employs link-list tables for buffer organization. In terms an hardware, EDVC input-port organization consumes on average 51% less power for ASIC design when compared with the CDVC input port. The saving is even good when compared with VC regulator methodology. This EDVC approach can improve NoC latency by 38%–48% and throughput by 100% on average as compared with the CDVC mechanism. The proposed design parameters are analyzed using Xilinx 9.1.

Authors and Affiliations

Praveen M, Mothi. R

Keywords

Related Articles

Fault Diagnosis and Monitoring In Wind Turbine Using Can Bus

This paper is a CAN based architecture intended for the purpose of monitoring and fault diagnosis of wind turbine. CAN is a memo based protocol designed specifically for automotive, late aerospace, industrial automation...

Structural Analysis of Bicycle Structure and Improvement Analysis using Analytical and Finite Element Analysis

Bicycles are the common man mode of transportation for centuries. They are environmentally friendly and remote places can be easily accessed where road conditions are bad. Since it is essential member of common people,...

Exam Evaluation System

the project is Examination scheduling or planning is a very crucial activity for any education and training institutes to conduct end-of-term examination which helps to optimize use of campuses rooms, time slot and tota...

A Novel Water Marking Scheme Using Feature Selection technique using Particle of Swarm Optimization

Digital watermarking techniques play an important role in privacy protection and copyright protection for multimedia data. In current research trend various watermarking technique are available such as spatial watermark...

Impact of Different Process Parameters on the Strength of Welded Joint in Friction Stir Welding

Friction stir welding process is used to combine high strength aluminum alloys, thermoplastic material and other metals also. In Friction stir welding high temperature results in excessive heat generation which ultimate...

Download PDF file
  • EP ID EP23922
  • DOI http://doi.org/10.22214/ijraset.2017.4216
  • Views 270
  • Downloads 9

How To Cite

Praveen M, Mothi. R (2017). Low Latency NoC Router Micro Architecture using Dynamic Virtual Channel Organization. International Journal for Research in Applied Science and Engineering Technology (IJRASET), 5(4), -. https://europub.co.uk/articles/-A-23922