Low Power Design of Standard Digital Gate Design Using Novel Sleep Transistor Technique

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Low Power Design of Standard Digital Gate Design Using Novel  Sleep Transistor Technique

Journal Title: International Journal of Modern Engineering Research (IJMER) - Year 2014, Vol 4, Issue 4

Abstract

In the nanometer range design technologies static power consumption is very important issue in present peripheral devices. In the CMOS based VLSI circuits technology is scaling towards down in respect of size and achieving higher operating speeds. We have also considered these parameters such that we can control the leakage power. As process model design are getting smaller the density of device increases and threshold voltage as well as oxide thickness decrease to maintain the device performance. In this article two novel circuit techniques for reduction leakage current in NAND and NOR inverters using novel sleepy and sleepy property are investigated. We have proposed a design model that has significant reduction in power dissipation during inactive (standby) mode of operation compared to classical power gating methods for these circuit techniques. The proposed circuit techniques are applied to NAND and NOR inverters and the results are compared with earlier inverter leakage minimization techniques. All low leakage models of inverters are designed and simulated in Tanner Tool environment using 65 nm CMOS Technology (1volt) technologies. Average power, Leakage power, sleep transistor

Authors and Affiliations

Kusum Tomar1 , A. S. M. Tripathi2

Keywords

Average power Leakage power sleep transistor.

EP ID EP152340
DOI -
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