Low Power Design Techniques in CMOS Circuits : A Review
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2015, Vol 3, Issue 2
Abstract
In the design of digital integrated circuits, power consumption is an important criterion. That indicates that low power circuits are now a days, emerging as an utmost priority in modern VLSI design. This is in contrast with the early 70s, when providing high speed operation with the least area was the main aim of design. But of course, other factors like area, propagation delay, leakage current etc. also can not be ignored in the design process. Out of these techniques, some are quite efficient in reducing static (leakage) power .This paper is prepared to review the available low power design techniques that are pivotal in designing various digital circuits.
Authors and Affiliations
Agrakshi Mehta, Suman Rani
Keywords
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