Macs: A Highly Customizable Low-Latency Communication Architecture
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2017, Vol 5, Issue 5
Abstract
Networks-on-chips (NoCs) are an increasingly popular communication infrastructure in single chip VLSI design for enhancing parallelism and system scalability. Processing elements (PEs) connect to a communication topology via NoC switches, which are responsible for runtime establishment and management of inter-PE communication channels. Since NoC switch design directly affects overall system performance and exploited communication parallelism, much previous work focuses on efficient NoC switch design. In this paper we present ‘MACS— a Minimal Adaptive routing Circuit Switching’ based switch for a two-dimensional mesh topology NoC highly parametric NoC switch architecture that provides reduced data transfer latency, increased designer flexibility, and scalability as compared to previous architectures by combining and enhancing several NoC design strategies. MACS enhances inter-PE communication using a circuit switching technique with minimal adaptive routing and a simple and fair path resolution algorithm to maximize bandwidth utilization. Our main idea is to avoid communication failures among the nodes and hence increasing the speed of processing and maintain throughput. The source code is written in Verilog. The designed router is synthesized in XILINX ISE 12.2 and simulation is carried out by using ModelSim 10.1 the design is implemented in Altrea Cyclone IV FPGA .
Authors and Affiliations
Ashwini P Mallipatil, S. Rekha, Vivekanand M Bonal
Keywords
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