Minimum Mismatch of Current in Fully Differential Charge Pump for Integer N- DPLL
Journal Title: International Journal of engineering Research and Applications - Year 2017, Vol 7, Issue 5
Abstract
Fully Differential ended charge pump (FDCP) are proven to have advantages over single ended charge pump at the cost of complexity and required more power for implementation for digital phase locked loop(DPLL). Wide swing cascodebias voltage with the rail to rail operational amplifier(opamp) as common mode feedback(CMFB) provides efficient solutions for current mismatch due to its non-idealities. The FDCP is simulated across process corners using 65nm technology with tsmc foundry for10Ghz DPLL. The power consumption of FDCP is 23mW with 100uA as Charge Pump (CP) current.
Authors and Affiliations
Rajeshwari D S, P V Rao
Keywords
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- EP ID EP391241
- DOI 10.9790/9622-0705041317.
- Views 128
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