Modified Reconfigurable CSD Fir Filter Design Using Look up Table
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2016, Vol 4, Issue 4
Abstract
Memory based structures are used in many kind of digital signal processing (DSP) applications, such as which involve in multiplication with a fixed set of coefficients. Memory-based structures are better performance in area minimization compare with multiply-accumulate structures and have many other advantages like reduced latency since the memory access time is much shorter than the usual multiplication time compared to the conventional multipliers. The multiplier uses LUT’s as memory for their computations. The anti-symmetric product coding (APC) and odd-multiple-storage (OMS) techniques were proposed for look-up-table (LUT) design. Simulation results show that this filter system has a good performance, the filter speed is higher and the resource occupation is fewer. The results of FPGA implementations increase of the maximum frequency, the decrease of the resources usage and the reduction of the dynamic power with a new proposed FPGA algorithm.
Authors and Affiliations
Sivakumar. M, Ranjitha. S, Vijayabharathi. P, Dhivya. G
Keywords
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