Multi Objective Analysis of Standard Cells Using Sense Amplifier Based QDI Approach
Journal Title: IOSR Journal of Electronics and Communication Engineering(IOSR-JECE) - Year 2018, Vol 13, Issue 4
Abstract
The main aim of this paper is to design various Quasi- Delay-Insensitive (QDI) Standard Cell Templates with more energy efficient techniques for asynchronous Circuit design. Out of these, Pre-Charged Half-Buffer (PCHB), Autonomous signal validity Half Buffer(ASVHB) and Sense Amplifier Half-Buffer (SAHB) cell design approaches are probable preferences for low power dissipation ,high speed of operation and high energy efficiency. The first cell design approach is Pre-Charged Half Buffer (PCHB) based on the use of domino logic; however it takes 74% transistor count in the circuit. The second design approach, ASVHB is an asynchronous QDI cell template operates at sub-threshold voltage for low power dissipation. The third design technique, SAHB is an asynchronous QDI cell template used to achieve high speed of operation and low energy and power dissipation. This paper presents seven library cells (i.e., a single input buffer, 2-input AND/NAND, 2-input XOR/XNOR, and 3-input AO/AOI) integrates PCHB, ASVHB, and SAHB design approaches. All the seven library cells are designed and implemented using mentor graphics 130nm technology. The performance attributes like delay, power dissipation,rise time,fall time,duty cycle, slewrate and energy are calculated and tabulated. It also promotes each template with precise characteristics that can be appropriate for low power and high-performance applications.
Authors and Affiliations
S. Jhansi Rani, Dr. J. Sudhakar
Keywords
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- EP ID EP439240
- DOI 10.9790/2834-1304015664.
- Views 137
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