Multilevel Power Estimation Of Benchmark Circuit Using Neural Algorithm
Journal Title: International Journal of Electronics Communication and Computer Technology - Year 2014, Vol 4, Issue 3
Abstract
Dissipation of power has emerged as one of the very important design constraints as the complexity of VLSI circuits has been increased. Now low power designs are generally preferred in various applications. In order to estimate the power consumption of the entire design correctly, an accurate memory power model is needed. In earlier days power estimation was made at the higher levels of design flow. Lookup table was the approach for power modeling, but lookup tables may become infeasible for large circuits because the table size would increase exponentially to meet the accuracy requirement. Multilevel power estimation is done at different levels of abstraction including the Register Transfer Level (RTL), the gate and the transistor level. These levels give the detailed information of the circuit. For complex digital circuits, building their power models is a popular approach to estimate their power consumption. The work introduces the power modeling approach using neural networks to learn the relationship between power dissipation and input/output characteristic vector during simulation. The neural power models have high accuracy because they can automatically consider the non-linear power distributions. More importantly our neural power model is very simple and straightforward and it does not require any transistor-level or gate-level description of the circuits
Authors and Affiliations
Sarita Chauhan| Head, Department of ECE M.L.V.T.E.C. Bhilwara Bhilwara (Rajasthan), India, Bhavesh Prajapat| Student, Department of ECE M.L.V.T.E.C. Bhilwara Bhilwara (Rajasthan),India
Keywords
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