16nm planar process CMOS SRAM cell design: Analysis of Operating Voltage and Temperature Effect
Journal Title: International Journal of Electronics Communication and Computer Technology - Year 2013, Vol 3, Issue 5
Abstract
Purpose: CMOS devices are scaling down to nano ranges resulting in increased process variations and short channel effects which not only affect the reliability of the device but also performance expectations. The SRAM design uses the smallest transistors possible and is also susceptible to reliability issues and process variations, making it an ideal benchmark circuit to compare the two technologies [1]. Low power static-random access memories (SRAM) have become a critical component in modern VLSI systems. They occupy a large portion of area and accounts for a major component of power consumption in today’s VLSI circuits. In this paper we intend to analyse the performance of a traditional 6T SRAM cell of 16nm Complementary Metal Oxide Semiconductor (CMOS) technology with change in Operating Voltage and Temperature. Aim: The aim of the paper is to study the effect of the SNM dependencies on the operating voltage and temperature Approach: Conventional 6T SRAM are designed using predictive technology model developed by Arizona State University [2] of 16nm planar Low Power CMOS and variation of SNM with operating voltage and temperature are simulated and studied using hspice. Findings: Variations in the operating voltages and temperature strongly impact the stability of an SRAM cell at 16nm. Comparative study is done for predictive 16nm based conventional 6T SRAM cell by varying operating voltage and temperature. A methodology to select operating voltage is suggested which can be used in an early stage of a design cycle to optimise stability margins in nanometer regime
Authors and Affiliations
Rohit Sharma| Reseach Scholar ECE Department, MMMEC, Gorakhpur, UP, India, R. K. Chauhan| Associate Professor ECE Department, MMMEC, Gorakhpur, UP, India
Keywords
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