Multistage Implementation of 64x Interpolator
Journal Title: International Journal of Advanced Research in Computer Engineering & Technology(IJARCET) - Year 2012, Vol 1, Issue 7
Abstract
This paper presents the design consideration and simulation of interpolator suitable for delta sigma D/A converter. The proposed structure uses the half band filer & Sinc filter using the MATLAB Tool. Experimental result shows that proposed interpolator achieves the design specification, and also has good noise rejection capabilities. The interpolator accepts the input at 44.1 kHz for applications like CD, SACD & DVD audio. The interpolation filter can be applied to the delta sigma DAC and is fully functional. To reduce the hardware requirement in terms of multiplier we used the Sinc filter whose structure is cascaded integration & combination (Multiplier free). The filter coefficients were generated with the help of MATLAB & the MATLAB generated (HDL Coder) VHDL code is synthesized in Xilinx ISE 13.1 for the Xilinx VERTEX6 FPGA chip. The achieved frequency of operation for the multistage 64x interpolator is 26.112 MHz. The experiment includes the simulation of the proposed interpolator for the sinusoidal signal with random noise.
Authors and Affiliations
Rahul Sinha, , Sonika Arora,
Keywords
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