An efficient model for design of 64-bit High Speed Parallel Prefix VLSI adder
Journal Title: International Journal of Modern Engineering Research (IJMER) - Year 2013, Vol 3, Issue 5
Abstract
To make addition operations more efficient parallel prefix addition is a better method. In this paper 64-bit parallel prefix addition has been implemented with the help of cells like black cell and grey cell operations for carry generation and propagation. This process gives high speed computations with high fan-out and makes carry operations easier. Xilinx 14.1 vivado tool has been used for the simulation of proposed 64-bit adder. The comparison can be made with the help various range of inputs and the proposed parallel prefix adder has produced high speed computation and also efficient in terms of number of transistors and their topology and number of nodes.
Authors and Affiliations
M. Mahaboob Basha
Keywords
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