An Improved Squaring Circuit for Binary Numbers
Journal Title: International Journal of Advanced Computer Science & Applications - Year 2012, Vol 3, Issue 2
Abstract
In this paper, a high speed squaring circuit for binary numbers is proposed. High speed Vedic multiplier is used for design of the proposed squaring circuit. The key to our success is that only one Vedic multiplier is used instead of four multipliers reported in the literature. In addition, one squaring circuit is used twice. Our proposed Squaring Circuit seems to have better performance in terms of speed.
Authors and Affiliations
Kabiraj Sethi , Rutuparna Panda
Keywords
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