Architectural Level Power Optimization Techniques for Multipliers
Journal Title: INTERNATIONAL JOURNAL OF ENGINEERING TRENDS AND TECHNOLOGY - Year 2012, Vol 3, Issue 5
Abstract
— In this work, a new topology was proposed to optimize the power dissipation of Multipliers. Low power digital Multiplier Design based on bypassing techniquemainly used to reduce the switching power dissipation. While this technique offers great dynamic power savings mainly in array multipliers, due to their regular interconnection scheme, it misses the reduced area and high speed advantages of tree multipliers. Therefore, mixed style architecture, using a traditional tree based part, combined with a bypass, array based part, is proposed. Prototyping of all these multiplier Architectures has been carried out on Spartan3E FPGA. By Evaluating the performance of these Multiplier architectures using Xilinx ISE tool suite , it has been found that while the bypass technique offers the minimum dynamic power consumption, the mixed architecture offers a delay*power product improvement , compared to all other architectures.
Authors and Affiliations
V. Alekhya#1, B. Srinivas*2
Keywords
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