Design and Simulation of a High Performance Multiplier using Reversible Gates
Journal Title: International Journal of Engineering Sciences & Research Technology - Year 30, Vol 3, Issue 6
Abstract
Multipliers are the significant part of the present technology as they are mostly used in the convolution, fast Fourier transform, CPU designing etc. The speed and power dissipation of the multiplier operation is the very important factor. The reversible logic design provide the low power dissipation hence the multiplier designed using the reversible logic gates provide the low power dissipation and also the high performance. In our design we use the reversible logic gates are BVPPG gate, BME gate and MHNG gate. Our design provides high performance and also dissipates the low power than any other reversible design.
Authors and Affiliations
Harish Raghavendra Sanu*
Keywords
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