Design of Low Density Parity Check Decoder for WiMAX and FPGA Realization
Journal Title: INTERNATIONAL JOURNAL OF ENGINEERING TRENDS AND TECHNOLOGY - Year 2013, Vol 4, Issue 5
Abstract
Error detection and correction is one of the most important blocks of a communication system. In order to achieve reliable communication over noisy channels with low power consumption, are used for error correction codes. Parity check codes low density are the most recent error correcting codes and are increasingly popular because of their excellent performance. As the performance of the codes is only fraction dB away from the boundaries of the channel capacity of these codes have become very popular and have become strong competitors to turbo codes. The emphasis in this work is the iterative decoding algorithms for LDPC codes for WiMAX standard and their hardware implementations. A software reference model is designed to LDPC codes with Min-Sum, Sum Regular and algorithms for all code rates the decoding in IEEE802.16estandard. A modified version of Min-Sum algorithm chosen hardware modeling of the LDPC decoder based on the performance results of the simulation software reference model. A GUI is designed to provide all algorithms, frame lengths and code rates together with a comparison of the performance and make records of the results easier. Hardware Models of check node and variable node and the switching network is designed to build a semi-parallel decoder in Verilog for frame length of 576 and 2304. An efficient semi-parallel decoder for LDPC codes is designed to optimize hardware implemented in Verilog FPGA.. Comparison of the outputs of software reference model for different algorithms clearly the performance loss in Min-Sum algorithm with reduced complexity. The hardware model implemented using Min-Sum algorithm is synthesized for implementation on Xilinx FPGA family Virtex2 XC2V40 device with input clock rate of 50MHz. The hardware design can handle a maximum frequency of 171.939MHz with a maximum delay of 4.840ns. Total equivalent gate count for the design is 8069 ports. The estimated Static power consumption of all logic and memory units in the design is about 333mW
Authors and Affiliations
M. K Bharadwaj #1, Ch. Phani Teja*2, K. S ROY
Keywords
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