High Performance and Power Efficient Comparator Using Scalable Parallel Prefix Tree
Journal Title: International Journal of Engineering Sciences & Research Technology - Year 30, Vol 3, Issue 3
Abstract
A new comparator design featuring of wide-range and high-speed using only digital CMOS cells. The comparator exploits a novel scalable parallel prefix tree structure that allows the comparison outcome of most significant bit, towards least significant bit when compared bits compared bits are equal .This method reduces dynamic power dissipation by eliminating unnecessary transitions. And a comparator with maximum fan-in and fanout of five and four respectively. The main advantages of this design are high speed and power efficient. Additionally this design uses a regular reconfigurable VLSI topology that allows input and output as a function of bit width. Simulation for 16-b comparator shows a total power consumption of 27mW using TSMC technology.
Authors and Affiliations
R. Krithika
Keywords
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- EP ID EP158818
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