Noise Tolerant and Faster On Chip Communication Using Binoc Model
Journal Title: International Journal of Modern Engineering Research (IJMER) - Year 2013, Vol 3, Issue 5
Abstract
Network on chip (NoC) has become the most promising and reasonable solution for connecting many cores in system on chips (SoC). In conventional NoC architectures neighbouring routers are connected via hard wired unidirectional communication channels. Due to unpredictable and uneven traffic patterns in NoC one of the channels maybe overflowed due to heavy traffic in one direction while the other unidirectional channel is idling and thus causing inefficient resource utilization, data loss and degradation in performance. So as a remedy for this situation a bidirectional NoC (BiNoC) can be used, which uses bidirectional channels to connect adjacent routers and it also supports runtime reconfiguration of channel direction according to traffic demand by using channel direction control (CDC) protocol. Since data communication through Network on Chip is susceptible to noise due to the presence of various noise sources, the incorporation of a hybrid error control scheme in which combined approach of error correction and retransmission is used which increases the reliability of the system. This architecture will allow the NoC structure to handle massive data transmission by effectively increasing the communication bandwidth, resource utilization capability and speed of NoC communication together with the increased reliability. The architecture is modelled using VHDL.
Authors and Affiliations
Arun Arjunan, Karthika Manilal
Keywords
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