Novel Implementation of Low Power Test Patterns for In Situ Test

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Novel Implementation of Low Power Test Patterns for In Situ Test

Journal Title: International Journal of Research in Computer and Communication Technology - Year 2015, Vol 4, Issue 11

Abstract

Test vector generation, its application to CUT and its response analysis are the tasks done by the In Situ Test. A new and efficient approach for the Generation of all one bit changing random input patterns for in situ test is developed in this paper using counter with gray. In this proposing technique, the counter with gray is used to generate all the 2n one bit change test vectors to overcome the limitations of existing two counters viz., Johnson counter and scalable SIC counter of n-bit size , because they consists of (2n-2n) unused test patterns. So this approach of in situ testing can be done with less power dissipation because switching power dissipation is reduced as we are applying one bit change binary test patterns. The developed test vector generation is suitable for both the test per clock and test per scan based BIST systems. We have carried the simulation and verified the results using ISE simulator and synthesis is done on the XILINX ISE.

Authors and Affiliations

K. Ramya, Y. N. S. VamsiMohan, S. V. S. M. Madhulika

Keywords

IN SITU test low power one bit change binary patterns test vector generator (TVG) Johnson counter scalable SIC counter counter with gray

EP ID EP28334
DOI -
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