Overcoming the Leakage Power Analysis Attack Using Higher Order DPA-Resistant AES-Masking
Journal Title: Scholars Journal of Engineering and Technology - Year 2016, Vol 4, Issue 6
Abstract
Abstract:The analysis of the effectiveness of Leakage Power Analysis (LPA) attacks to cryptographic VLSI circuits on which circuit level countermeasures against Differential Power Analysis (DPA) are adopted. Security metrics used for assessing the DPA-resistance of crypto core implementations is AES encipher and decipher operations and masking is a common method used to prevent differential power analysis (DPA) attack. First, reordering the execution sequence of SubBytes and ShiftRows and partition new critical path of the masked SubBytes followed by the masked MixColumns, and transform computations from GF (28) to GF (24)2 that efficiently reduces the area. Second, developing an algorithm to search for an optimal transformation matrix of the map function to reduce the critical path of the masked Mix Columns. Third, reusing first order masked SubBytes for higher order masked SubBytes to optimize area without compromising performance. The LPA attacks can be successfully carried out on Higher Order DPA-Resistant AES in presence of process variations. Keywords:Leakage Power Analysis (LPA), Differential Power Analysis (DPA), SubBytes, ShiftRows.
Authors and Affiliations
Malini S, Manju Priya K, Shiney Immaculate S
Keywords
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