Performance Analysis Of Vedic Multiplier Using Reversible Logic In Spartan 6

Abstract

A system's performance is generally determined by the performance of the multiplier, because the multiplier is generally the slowest element in the system. Multipliers are key components of many high performance systems such as FIR filters, Microprocessors, Digital Signal Processors, etc. Furthermore, it is generally the most area consuming. Hence, optimizing the speed and area of the multiplier is a major design issue. Vedic multiplier is one such promising solution. Vedic mathematics is the name given to the ancient Indian system of mathematics that was rediscovered in the early twentieth century from ancient Indian sculptures (Vedas). This paper proposes the design of high speed Vedic Multiplier using the techniques of Vedic Mathematics that have been modified to improve performance. Its simple architecture coupled with increased speed forms an unparalleled combination for serving any complex multiplication computations. Tagged with these highlights, implementing this with reversible logic further reduces power dissipation. Power dissipation is another important constraint in an embedded system which cannot be neglected. In this paper we bring out a Vedic multiplier known as "Urdhva Tiryakbhayam" meaning vertical and crosswise, implemented using reversible logic, This paper presents study on high speed Vedic multiplier architecture which is quite different from the Conventional method of multiplication like add and shift. Further, the HDL coding of Urdhva tiryakbhyam Sutra for 8x8 bits multiplication and their FPGA implementation by Xilinx Synthesis Tool on Spartan 6 kit have been done and output has been displayed on LED’s of Spartan 6 kit. Logic verification of these modules has been done by using Modelsim 6.5.bThis multiplier may find applications in Fast Fourier Transforms (FFTs), and other applications of DSP like imaging, software defined radios, wireless communications.

Authors and Affiliations

T Nagaveer, M Neelima, VNM Brahmanandam

Keywords

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  • EP ID EP28063
  • DOI -
  • Views 250
  • Downloads 0

How To Cite

T Nagaveer, M Neelima, VNM Brahmanandam (2014). Performance Analysis Of Vedic Multiplier Using Reversible Logic In Spartan 6. International Journal of Research in Computer and Communication Technology, 3(10), -. https://europub.co.uk/articles/-A-28063