Performance Analysis Of Vedic Multiplier Using Reversible Logic In Spartan 6

Abstract

A system's performance is generally determined by the performance of the multiplier, because the multiplier is generally the slowest element in the system. Multipliers are key components of many high performance systems such as FIR filters, Microprocessors, Digital Signal Processors, etc. Furthermore, it is generally the most area consuming. Hence, optimizing the speed and area of the multiplier is a major design issue. Vedic multiplier is one such promising solution. Vedic mathematics is the name given to the ancient Indian system of mathematics that was rediscovered in the early twentieth century from ancient Indian sculptures (Vedas). This paper proposes the design of high speed Vedic Multiplier using the techniques of Vedic Mathematics that have been modified to improve performance. Its simple architecture coupled with increased speed forms an unparalleled combination for serving any complex multiplication computations. Tagged with these highlights, implementing this with reversible logic further reduces power dissipation. Power dissipation is another important constraint in an embedded system which cannot be neglected. In this paper we bring out a Vedic multiplier known as "Urdhva Tiryakbhayam" meaning vertical and crosswise, implemented using reversible logic, This paper presents study on high speed Vedic multiplier architecture which is quite different from the Conventional method of multiplication like add and shift. Further, the HDL coding of Urdhva tiryakbhyam Sutra for 8x8 bits multiplication and their FPGA implementation by Xilinx Synthesis Tool on Spartan 6 kit have been done and output has been displayed on LED’s of Spartan 6 kit. Logic verification of these modules has been done by using Modelsim 6.5.bThis multiplier may find applications in Fast Fourier Transforms (FFTs), and other applications of DSP like imaging, software defined radios, wireless communications.

Authors and Affiliations

T Nagaveer, M Neelima, VNM Brahmanandam

Keywords

Related Articles

A Glance At Malicious Attacks In Web

Web usage is one of the great important to all users in this era. For each and every need internet or web is made use of. Users make use of the area as a medium for searching information, performing business transacti...

Comparative Study of Hand Gesture Recognition Algorithms

Gesture recognition is the technique which is employed for the interaction between human and computer or any auto. In this paper, different types of gesture recognition algorithm is being proposed. Hand detection and...

Swastika shaped Monopole Antenna with Stubs for Cognitive radio Applications

The proposed antenna designed specifically for Cognitive radio applications consists of a circular monopole which is modified and evolved into the Swastika shaped dotted monopole by incorporating slots into the plane...

Minimizing Packet Delay Rate in Tree based wireless sensor networks

In this advanced and fast world people do not want to wait much for collecting information. Hence now a day’s collecting information in a faster way became a challenge for the researchers. Faster data collection in W...

Design and Development of Gesture Controlled MP3 Player Using ARM7 and Image Processing Technique

The aim of the project we are controlling the MP3 Player by Gesture. A Gesture image is taken from Camera and image will be processing in MATLAB and using the human hand movement the image is recognized and depending...

Download PDF file
  • EP ID EP28063
  • DOI -
  • Views 232
  • Downloads 0

How To Cite

T Nagaveer, M Neelima, VNM Brahmanandam (2014). Performance Analysis Of Vedic Multiplier Using Reversible Logic In Spartan 6. International Journal of Research in Computer and Communication Technology, 3(10), -. https://europub.co.uk/articles/-A-28063