Power Dissipation Reduction In CMOS Circuits Using Power Gating Scheme
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2013, Vol 2, Issue 12
Abstract
In this paper by victimization power gating technique we tend to reduced the discharge power of the Conditional information Mapping Flip-flop .In, this gift days low power technology is increasing chop-chop, majorly circuits was accomplished by the discharge power due varied scaling techniques applied on the circuits to scale back the realm occupancy of the circuit that in deed will increase the ability dissipation of the circuit. That discharge power was reduced victimization completely different power gating circuits. Here we tend to simulate our circuits victimization DSCH and small wind.
Authors and Affiliations
D. Abhilash Sharon ,M. Santhosh Gideon
Keywords
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