Power Reduction in Sub-Threshold Dual Mode Logic Circuits

Journal Title: UNKNOWN - Year 2015, Vol 4, Issue 3

Abstract

Power dissipation has always been a major concern in integrated circuit design. Even during static state, there is a small amount of leakage power. In this project we have implemented the Sub threshold Dual mode logic in CMOS basic gates and 2- bit Full Adder. This logic can bring down the total power. Hence a comparative analysis of power consumption is performed between conventional and Sub threshold dual modes. The logic has two modes of operation namely Static and Dynamic. In Static mode, there is a considerable decrease in the power consumed along with a moderate performance. Dynamic mode renders high performance compromising on an increase in power consumption. The power is evaluated using Tanner Simulation tool under 180nm technology.

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  • EP ID EP356972
  • DOI -
  • Views 74
  • Downloads 0

How To Cite

(2015). Power Reduction in Sub-Threshold Dual Mode Logic Circuits. UNKNOWN, 4(3), -. https://europub.co.uk/articles/-A-356972