Reconfiguration of Memory for High Speed Matrix Multiplication
Journal Title: International Journal of Advanced Research in Computer Engineering & Technology(IJARCET) - Year 2013, Vol 2, Issue 5
Abstract
The paper entitled “RECONFIGURATION OF MEMORY FOR HIGH SPEED MATRIX MULTIPLICATION“ is basically an enhancement in speed of matrix multiplication. The project aims at reducing the time involved in the operation. The system presented here makes use of three RAMS designated as MAT-RAM-A, MAT-RAM-B and MAT-RAM-C and system also consists of a control circuitry. This system works in two modes i.e., mode-1 and mode-2. In mode-1 the RAM’s act as extensions of existing memory of the processor and in mode-2 the two RAMs MAT-RAM-A and MAT-RAM-B are configured as source for hardware with MAT-RAM-C working as destination for storage or resultant matrix after multiplication. The RAMs are configured back in mode-1, so that data can be read from MAT-RAM-C.
Authors and Affiliations
Ms. Shamshad Shirgeri , Ms. Pallavi Umesh Naik , Mrs. Rohini , , Prof. Krishnananda Shet
Keywords
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- EP ID EP151704
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