RTL Level and Self-Test Approach Based Arithmetic BIST
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2015, Vol 3, Issue 10
Abstract
In this paper an accumulator-based 3-weight test pattern generation scheme is presented. First, it does not impose any requirements about the design of the adder i.e., it can be implemented using any adder design and then it does not require any modification of the adder; and hence it does not affect the operating speed of the adder. Furthermore, the proposed scheme compares favourably to the scheme proposed in terms of the required hardware overhead. The weighted random test pattern generation represents a significant departure from classical methods of generating test sequences for complex large scale integration packages. The virtue of this technique is its simplicity and the fact that test-generation time is virtually independent of gates in the logic package to be tested. This technique can be used both in a conventional tester and in a tester where the weighted random test pattern generation is implemented in hardware. By this proposed method the patterns are generated with reduced delay.
Authors and Affiliations
Shaik Anjumra, P. Bala Murali Krishna
Keywords
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- EP ID EP21294
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