Skew Managed Global Clock Network Using Type Matching
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2016, Vol 4, Issue 12
Abstract
Clock gating has emerged as an effective low power technique these days. Various researches are being made in the optimization of this technique. While clock gating finds its applications in the clock tree synthesis, it’s crucial that this additional circuitry does not include skew to the entire chip design. Also when the clock gating involves the use of all gates, (i.e.) NAND, NOR which has different timing behaviours, there is a definite possibility of an increase in skew. Therefore, in this paper a global clock tree design called type matching is proposed, wherein same type of gate at every level of clock tree is maintained, replacing even the buffers with the same type of gate buffers with the proposed mechanism. Also a comparison on the normal clock gated tree and type matched clock tree is done and proved that the clock skew minimization is achieved in type matched clock trees at the cost of clock tree area and power consumption.
Authors and Affiliations
Jeba Saral Darling, Jessintha D
Keywords
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