Techniques of Power Phase-Noise Optimization of 2.4 / 4.8 GHz CMOS VCO with Switched Capacitor Array Using Bondwire Inductor
Journal Title: Bonfring International Journal of Power Systems and Integrated Circuits - Year 2013, Vol 3, Issue 3
Abstract
This paper presents theoretical analysis of the maximum operating frequency of proposed Source Degeneration (SD) and Conventional CML D-Latch are estimated. The approach is based on the voltage transfer function, which is derived from small signal model of the circuit. Design approach with pre and post layout simulation results have been presented in detail and compared the performance in terms of power consumption, self oscillation frequency, sensitivity and supply voltage. With example shows the, all pMOS Voltage Controlled Oscilaator (VCO) with MOS capacitor switched capacitor array (SCA) generates the high frequency sinewave reference signals fed in to both divider for to get quadrature (Q) sinewave signals. Off Chip Bondwire inductor is used instead of on chip spiral inductor in all-pMOS VCO as it have high quality factor. Also, it will neglect the variations of carrier frequency and it gives additional performance like phase noise, power consumption, area than using spiral inductor. Even if use spiral inductor in all-pMOS VCO, Bondwire inductor also presents due to low impedance path between drain and ground terminal. Various optimization techniques are implemented while designing a QVCO, which facilitates is used to achieve a low power low phase noise performance. Compared to other types of QVCO, the conventional QVCO shows good phase noise performance than normally achieved 6 dB phase noise improvement with carrier frequency. The simulated results shows about 5 dB, 4 dB, 4 dB and 4 dB of phase noise improvement at 10 kHz, 100 kHz, 1 MHz and 3 MHz offset frequency from the 2.4 GHz carrier frequency. This combinational topology doesn?t consume additional power and area than others and shows with improved phase noise performance. The pre and post layout simulation results are compared of both proposed (SD) and conventional QVCO, which is designed in 180 nm CMOS technology as 1V.
Authors and Affiliations
P. Arivazhagan
Keywords
Related Articles
- EP ID EP110379
- DOI 10.9756/BIJPSIC.10236
- Views 98
- Downloads 0
One of Two Conductors in Capacitor Substitute by Mercury
Each capacitor generally consists of two conductors separated by a non-conductive region, however a great changed happened in the modern capacitors but the principle has been remained the same as the first day designed....
Wireless Embedded System for Power Line Monitoring
The present day power systems combine various modes of generation, transmission and conversion. There is no unique system of monitoring the power frequency, faulted switching condition or the conversion switching phenome...
Overall Control Strategy of Grid Connected to Wind Farm Using FACTS
Wind energy is attracting more attention from researchers and even utilities due to its benefits as a clean and abundant source of energy. In this paper a comprehensive and intensive study of a wind farm connected to the...
PSO Based Optimal Placement and Setting of FACTS Devices for Improving the Performance of Power Distribution System
Power systems, under heavily loaded conditions, are at high risks of probable line outage and consequent voltage instability problem. Real power loss and voltage deviation minimization are reliable indicators of voltage...
Sustainable Programs for Inclusion of Low Income Customers and Energy Efficiency Education
Developing countries, especially the BRICS (Brazil, Russia, India, China and South Africa) set off a process of economic development and social inclusion, leading to the creation of a burgeoning middle class eager and ab...