Timing Analysis of Generic Multipliers
Journal Title: IOSR Journal of Electronics and Communication Engineering(IOSR-JECE) - Year 2018, Vol 13, Issue 1
Abstract
Multiplications are very expensive process and slow the overall operation. The performance of many computational problems is often dominated by the speed at which a multiplication operation can be executed. A multiplier is one of the key hardware blocks in most digital signal processing (DSP) systems. In DSP applications, multiplier plays a vital role include digital filtering, digital communication and spectral analysis.(Ayman.A et al (2001)).The aim of this paper is to present analysis of generic multipliers on the basis of timing performance. The generic architecture of all the four multipliers i.e. array, column bypass, wallace tree and booth multiplier has been analysed. Analysis of these multipliers tells that Wallace tree occupy more area but also faster than the other. The simulation and synthesis have been carried out on ISE design suite-14.9. By using this analysis different multipliers can be used for different applications in which timing performance is constraint.
Authors and Affiliations
Anju Rajput
Keywords
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- EP ID EP438964
- DOI 10.9790/2834-1301022938.
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