Universal Asynchronous Receiver and Transmitter Implementation on 40nm Technology
Journal Title: International Journal of Electronics Communication and Computer Engineering - Year 2018, Vol 9, Issue 2
Abstract
This paper presents the design of Universal Asynchronous Receiver and Transmitter module using various tools available in Cadence Design Systems and Xilinx namely: Cadence RC compiler, Cadence Encounter and Xilinx Design Suite 14.1i . Test bench simulation has been performed using the Xilinx Design in combination with Model Sim6.5e, while worst path analysis, power and timing analysis have been performed in Cadence RC Compiler. A UART module mainly consists of three components, a Transmitter, a Receiver, and a BAUD Rate Generator. A BAUD Rate Generator generates the clock for the Receiver and Transmitter. A BAUD rate is the symbol rate i.e. data rate thus higher the rate higher is the speed. For this simulation and analysis, we have use a baud rate of 9600 and the technology used is 40nm. For FPGA implementation a clock frequency of 25MHz has been used, and for slack timing and worst path analysis time periods ranging from 1000000ps to 1000ps, thus giving a frequency range of 100MHZ to 1GHz. NC Simulator is used for pre-simulation and post simulation which is done using the generated Netlist from Cadence and the 40nm Front End library from Cadence. For frequency analysis Cadence RC Compiler is used to generate schematic on a 40nm technology. Cadence SoC Encounter is used for the layout for optimization and routing
Authors and Affiliations
Satyendra Kumar, et al.
Keywords
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