VLSI Hardware Modelling Of Multifunction GF Architecture for Cryptographic Devices
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2015, Vol 3, Issue 6
Abstract
this paper presents a hardware structure for polynomial binary-to-residue number system (PRNS) conversion using parallel field structures. This structure is based only on polynomial multipliers along with GF architecture. This concise work is motivated by the existing RNS binary-to-RNS converters, which are particular inefficient for larger values of n. The experimental results obtained for a given dynamic range suggest that the projected conversion structures are able to drastically progress the forward conversion efficiency, with greater successful hardware modeling. And GF (Galois Field) can highly increase proper selection and utilization of the polynomial functions for high end applications like Cryptography. The proposed logistic technique is simulated and verified by Xilinx tools along with Virtex – 5 FPGA board.
Authors and Affiliations
Ramya P, Keerthi. N
Keywords
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- EP ID EP21011
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