A Novel Multiplier Design Using Adaptive Hold Logic to Mitigate BTI Effect Journal title: GRD Journal for Engineering Authors: A. Gopivignesh, P.N. Sundararajan Subject(s):
Low Power Variable Latency Multiplier With AH Logic Journal title: International Journal of Science and Research (IJSR) Authors: Subject(s):
VLSI Modeling of High Performance Aging Aware Multiplier By Using Adaptive Hold Logic Circuit Journal title: International Journal of engineering Research and Applications Authors: P. Lokesh, U. Somalatha, S. Chandana Subject(s):
