Clock Power Reduction Using Merged Flip Flops Technique Journal title: International Journal of Engineering Sciences & Research Technology Authors: S.Murugan Subject(s):
A Survey about Power Reduction in Intergated Circuits Using Multi-Bit Flip-Flops Journal title: International Journal of Engineering Sciences & Research Technology Authors: R.Rajakumari Subject(s):
Optimization of Region and Power with Routability Constrained Flip Flop Joining Process Journal title: Elysium Journal of Engineering Research and Management Authors: Mohamed Noor A., Abu Hanifa V. Subject(s):
