A Design Of A Low Power Delay Buffer Using Ring Counter Addressing Schemes
Journal Title: The International Journal of Technological Exploration and Learning - Year 2013, Vol 2, Issue 2
Abstract
This work presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flipflops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. A novel gatedclock-driver tree is then applied to further reduce the activity along the clock distribution network. Moreover, the gated-drivertree idea is also employed in the input and output ports of the memory block to decrease their loading, thus saving even more power.
Authors and Affiliations
B. R. B Jaswanth| St.Theresa Institute of Engineering and Technology Gudiwada, India, R. V. S Rayudu| V.K.R, V.N.B & A.G.K College of Engineering Gudiwada, India, K. Mani babu| V.K.R, V.N.B & A.G.K College of Engineering Gudiwada, India, R. Himaja| V.K.R, V.N.B & A.G.K College of Engineering Gudiwada, India, L. Veda kumar| V.K.R, V.N.B & A.G.K College of Engineering Gudiwada, India
Keywords
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- EP ID EP8472
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