Analysis of Carry Select Adder using Different Logic Styles
Journal Title: GRD Journal for Engineering - Year 2017, Vol 2, Issue 9
Abstract
Carry Select Adder (CSLA) is one of the fastest adder used to perform fast arithmetic operations. In our project, a modified carry select adder is designed by using single Ladner-Fischer (LF) and binary to Excess-1 Converter (BEC) instead of using dual RCA’s to reduce the area and delay. The correct sum and carryout signals will be selected by a set of multiplexers. LF adder is a parallel prefix form of carry look-ahead adder (CLA). It is the fastest adder with focus on time and is the common choice for high performance adders in industry. The better performance of LF adder is because of its minimum logic depth and bounded fan-out. In the proposed CSLA, one ripple carry adder (RCA) fed with Cin=0 is replaced by LF adder. The performance of proposed CSLA is analyzed and compared against CSLA design using RCA and BEC. The number of gates used in proposed CSLA is fewer than the CSLA using RCA and BEC. The result shows that area of proposed method is reduced by 25% and delay is reduced by 14%.
Authors and Affiliations
Fincy Mol, Saranya Tv, Shalini M
Keywords
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